This invention relates to electro-static-discharges (ESD) protection circuits, and more particularly to reducing latch-up susceptibility of ESD-protection structures.
Small electronic devices such as integrated circuits (IC) are prone to damage and failure from electro-static-discharges (ESD). Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors and thick-oxide transistors.
Another type of ESD structure uses an active transistor to safely shunt ESD current. Such an active ESD structure is especially useful for power-to-ground ESD zaps, where the ESD pulse is applied between a power pin and a ground pin. One or more special VDD-to-VSS ESD clamps can be added to the IC. These VDD-to-VSS clamps can turn on when an ESD pulse is applied between the power and ground pins. Sometimes charge from a pin-to-ground, pin-to-VDD, or pin-to-pin ESD zap may charge the internal power or ground buses. The active VDD-to-VSS clamp can turn on to discharge such charge build up, preventing damage deep inside the IC chip.
FIG. 1 shows a prior-art active ESD-protection circuit. Power node 62 is connected to a power supply pin such as VDD. Ground bus 60 is connected to a ground pad. During normal powered operation, the top plate of capacitor 30 is charged to VDD through resistor 20 from power node 62. The high voltage on node 63, the gates of transistors 10, 40 turns on n-channel transistor 40 and turns off p-channel transistor 10, causing the gate of n-channel shunt transistor 50 to be driven low. This keeps n-channel shunt transistor 50 turned off, allowing power node 62 to remain at VDD to power internal circuits.
When an ESD zap or pulse is applied to power node 62, or is somehow coupled into power node 62, such as through a common-discharge line (CDL), the rapid rise in voltage on node 62 causes the source of p-channel transistor 10 to rise quickly. The gate of p-channel transistor 10 does not rise as quickly because of the R-C time constant delay caused by charging of capacitor 30 through resistor 20. The gate-to-source voltage across p-channel transistor 10 increases in absolute value, causing p-channel transistor 10 to turn on. P-channel transistor 10 then charges the gate of n-channel shunt transistor 50 by connecting it to power node 62. The high voltage applied to the gate of n-channel shunt transistor 50 turns it on so that n-channel shunt transistor 50 shunts the ESD current from power node 62 to ground bus 60.
As current slowly flows through resistor 20 to charge the top plate of capacitor 30, the voltage on the gates of transistors 10, 40 rises. Eventually p-channel transistor 10 turns off and n-channel transistor 40 turns on, discharging the gate of n-channel shunt transistor 50 and turning it off. Also, as n-channel shunt transistor 50 discharges power node 62, eventually the magnitude of the gate-to-source voltage of p-channel transistor 10 falls below threshold, turning p-channel transistor 10 off.
While such an active VDD-to-VSS clamp is useful, a secondary problem can occur with the clamp circuit. Latch-up can be caused by the clamp circuit. FIG. 2 is a cross-section diagram of the VDD-to-VSS clamp circuit of FIG. 1. Metal lines in layers above the silicon substrate form most of ground bus 60 and power node 62. The VDD-to-VSS clamp is connected between these two nodes. The VDD-to-VSS clamp includes n-channel shunt transistor 50, n-channel transistor 40, p-channel transistor 10, capacitor 30, and resistor 20. I/O pad 70 is an un-related input/output pad connected to N+ region 66 in p-substrate 64.
N-channel shunt transistor 50 is formed by a gate over the channel between n+ regions 56, 54 in p-substrate 64. Power node 62 connects to drain n+ region 56 while ground bus 60 connects to source n+ region 54 and to p+ tap 52. N-channel transistor 40 is also formed by a gate connected to trigger node 63 over the channel between n+ regions 44, 46. Source n+ region 44 connects to ground, as does p+ tap 42, while drain n+ region 46 connects to the gate of n-channel shunt transistor 50.
P-channel transistor 10 is formed in N-well 12. N+ tap 14 and source p+ region 16 connect to power node 62, while p+ drain region 18 connects to the gate of n-channel shunt transistor 50. Resistor 20 is formed in another N-well 22, between n+ taps 24, 26. The relatively high resistance of the N-well produces the resistor's resistance. A serpentine pattern may be used to increase the length and decrease the width of N-well 22, increasing the total resistance.
Capacitor 30 is formed by the gate oxide between the gate connected to trigger node 63 and the N+ regions 34, 36 in p-substrate 64, which are connected to ground bus 60. P+ tap 32 is also connected to ground bus 60.
A latch-up problem can occur with this VDD-to-VSS clamp circuit. FIG. 3 highlights a potential latch-up trigger in the VDD-to-VSS clamp circuit. When a negative voltage below the ground voltage of ground bus 60 is applied to I/O pad 70, n+ region 66 can become forward biased. Electrons are injected from n+ region 66 into p-substrate 64. These injected electrons will be collected by N-well 22 of resistor 20, or by N-well 12 of p-channel transistor 10.
Electrons collected by N-well 22 may cause a voltage drop along resistor 20, especially when resistor 20 has a larger resistance value when a smaller current can create a larger voltage drop. This voltage difference along resistor 20 causes trigger node 63 to fall below power node 62, VDD. Once trigger node 63 falls more than a threshold below VDD, p-channel transistor 10 can turn on, since its gate is trigger node 63. The gate of n-channel shunt transistor 50 is driven higher, causing n-channel shunt transistor 50 to turn on. Large currents are drawn from power node 62 to ground bus 60. Temperature in p-substrate 64 will increase due to the high current. These large currents can cause voltage drops along power line 62, inducing VDD/GND line potential instabilities. Due to the large size of shunt transistor 50, a large amount of hot electron injection can occur from the high-field channel region close to the drain in n-channel shunt transistor 50 which leads to a large substrate current. It is well known that high silicon temperature, VDD/GND line potential fluctuations, and large substrate currents make latchup events more likely to occur.
A voltage drop across resistor 20 in N-well 22 can thus indirectly trigger a latchup event. Improved layout such as increased spacing and additional p+ taps to p-substrate 64 around n+ region 66 can reduce latch-up susceptibility, but additional taps and guard rings can occupy a significant area of the IC die.
What is desired is a reduction in susceptibility to latch up in an active VDD-to-VSS ESD clamp circuit. An active circuit technique to reduce latch-up susceptibility of the VDD-to-VSS clamp is desirable.